The first FPGA with programmable logic cells and programmable routing was described by Freeman in U.S. Pat. No. Re. 34,363, which is incorporated herein by reference. An FPGA includes configurable logic blocks and configurable routing, which are programmed by configuration memory cells. The configuration memory cells are typically arranged in an array and are loaded with a bit stream of configuration data. The configuration data is selected to cause the FPGA to perform a desired function.
FIG. 1 shows a conventional array of configuration memory cells (i.e., a configuration memory) such as used by Xilinx, Inc., assignee of the present invention. The configuration memory of FIG. 1 is a 16-bit by 16-bit array that includes 256 configuration memory cells. In general, each of the configuration memory cells is identified by a reference character Mx-y, where x and y correspond to the row and column of the configuration memory cell. A typical array of configuration memory cells in a commercial device has on the order of 20,000 to one million memory cells. Thus, the array of FIG. 1 is much smaller than is typically used in a commercial embodiment, but nevertheless shows the structure of prior art configuration memories. To load the configuration memory, the bit stream of configuration data is shifted through a data shift register DSR under control of a clocking mechanism (not shown), until a frame of data (16 bits wide in this example) has been shifted into bit positions DS0 through DS15 of the data shift register DSR. This frame of data is then shifted in parallel on lines D0 through D15 into a column of configuration memory cells addressed by address shift register ASR. Typically, some configuration memory cells are missing from the rows and columns. Missing memory cells are often due to idiosyncrasies in the layout of the configuration memory, or to the lack of need for a particular configuration memory cell in a desired logic scheme that still requires a rectangular array for implementation. Dummy bits are inserted into the bit stream as place holders for these missing memory cells. The column is addressed by shifting a token high bit through the address shift register ASR from bit AS0 to bit AS15, one shift per frame. Each time a frame of configuration data is loaded through data shift register DSR, it is loaded in parallel to the column of memory cells selected by the token high bit. When the token high bit shifts out to the right, it activates a DONE circuit, which indicates that configuration is complete and causes the FPGA to become operational.
In a typical FPGA, configuration data is shifted serially into a data shift register, then loaded in parallel into the configuration memory cells. In certain conventional parallel configuration modes, configuration data is loaded onto the device in parallel, and is then serially loaded into a data shift register.
The Xilinx XC5200.TM. family of FPGAs has a configuration mode called Express mode, in which configuration data is loaded in parallel (i.e., eight bits at a time) into a data shift register. (See "The Programmable Logic Data Book", pp. 4-54 to 4-78, published July 1996 by Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, hereinafter referred to as the "Xilinx 1996 Data Book".) The Express mode enables a configuration bit stream to be loaded at eight times the rate of the above-described conventional configuration modes. However, Express mode is limited to a single bus width of eight bits. Moreover, the configuration bit stream used in Express mode is not compatible with the configuration bit streams used to configure an XC5200 FPGA in other configuration modes (e.g., a serial configuration mode).
A purchaser of an FPGA may spend days, weeks, or months developing and perfecting a logic design to be implemented by the FPGA and generating the accompanying configuration bit stream to program the FPGA. Companies such as Xilinx, Inc., which manufacture FPGAs and other programmable devices, continue to develop new device architectures (or device families) with new features. Yet these companies continue to sell devices from the older device families because customers would rather use these older devices than repeat or augment the engineering necessary to generate a different configuration bit stream, which is required to cause a newer device to perform the same function as the older device. This means that the FPGA manufacturer must maintain an inventory of an increasing number of device families and maintain the capability to manufacture many device families. However, operating in this manner is inefficient for the FPGA manufacturer. It would therefore be desirable to make the older device families obsolete, thereby minimizing the number of device families that must be held in inventory. It would also be desirable to minimize the number of device families being manufactured in order to optimize manufacturing capacity. It would further be desirable for newer device families to be programmable with the same configuration bit streams as older device families.
One reason new device architectures are continuously arriving on the market is the desire among users for increased device flexibility, size, and speed. Partial reconfigurability, flexible pin allocation, and modified device layout for increased speed are just a few of the innovations only recently introduced to the FPGA marketplace.
While available memory-addressing mechanisms provide certain advantages in writing configuration data, there are a number of disadvantages in existing devices, including the difficulty of testing the devices before shipping to users because of the slow read speed of available configuration memory cells. FIG. 1A is a schematic diagram of a conventional five-transistor configuration memory cell M0-0 that includes one access transistor T1 and two CMOS inverters I1 and I2. As is well known in the CMOS design art, each of the two inverters I1 and I2 comprise one PMOS transistor and one NMOS transistor connected in series between power and ground. Inverters I1 and I2 are connected into a loop, thereby forming a latch. This latch is connected to a data line D0 by a pass transistor T1 that is controlled by address line A0. A line Q or QB (or both) extends from memory cell M0-0 to the FPGA logic structure (not shown) to control configuration. Such a structure is described by Hsieh in U.S. Pat. Nos. 4,750,155 and 4,821,233. As used in existing devices, this cell structure enables only relatively slow data readback capability, with a maximum speed for some devices of only 1 MHz. For a discussion on existing readback circuitry, see "The Programmable Logic Data Book", pp. 8-17 to 8-24, published 1993 by Xilinx, Inc. (hereinafter referred to as the "Xilinx 1993 Data Book"). It would therefore be desirable to be able to rapidly read configuration memory cells.